1. Field of the Invention
Apparatuses and methods consistent with the present invention relate to detecting time, and more particularly to a high resolution time detecting apparatus using an interpolation and a time detecting method thereof.
2. Description of the Related Art
Advanced semiconductor processing has increased speed of transistors and decreased supply voltages. As the decrease in supply voltage increases sensitivity of analog circuit, more and more circuits are designed in digital domain rather than the previous analog domain. A phase locked loop (PLL) is one example.
A PLL generally refers to the circuits that obtain stable oscillation outputs at the same frequency as a reference signal by use of a negative feedback circuit. A PLL generally includes a phase comparator that compares and detects a phase difference between an input frequency as a reference and an output from a voltage controlled oscillator (VCO), a low band loop filter that removes high frequency component and determines synchronization or response characteristic of a PLL, a frequency divider, and the VCO that changes frequency linearly with reference to a DC voltage applied. By the term ‘phase locked,’ it means that an output frequency completely matches an input frequency, except for a different phase.
However, change of analog PLL to digital brought about a problem that a high frequency signal of VCO is not converted into a digital signal to a satisfactory resolution.
As a result, a method is required, which improves performance of a digital PLL to output high resolution digital signal with low power consumption, and without compromising compactness of an integrated circuit.